1. Field of the Invention
The present invention relates to a multi chip package (MCP) in which first and second semiconductor chips are mounted on a same MCP substrate. In particular, the present invention relates to the MCP in which the second semiconductor chip can be diagnosed independently of the first semiconductor chip, and a method of measuring the electrical characteristics of the second semiconductor chip mounted on the MCP.
2. Description of the Related Art
In recent years, an MCP in which a CPU chip (first semiconductor chip) and an intellectual property (IP) chip (second semiconductor chip) are mounted on an MCP substrate has come to the front. The CPU chip serves as a main and pivotal control chip and configured to perform miscellaneous information processing. And the IP chip exchanges signals with the CPU chip to perform a specific function. In the MCP of this type, the number N.sub.MCP of pins of the MCP is limited by: EQU N.sub.MCP =N.sub.CPU -N.sub.IP (1)
Where N.sub.CPU is the number of pins of the CPU chip, and N.sub.IP is the number of pins of the IP chip. When the MCP is viewed from the outside, only the CPU chip can drive and access the IP chip. More specifically, in the conventional MCP, terminals configured such that the IP chip can directly exchanges signals with an external circuit are not formed. Therefore, in the conventional MCP, the IP chip cannot directly receive signals from the external circuit, nor CPU chip cannot directly feed signals to the external circuit without using the interconnections and internal circuitry formed on the CPU chip.
In this manner, in the conventional MCP, signals must be supplied to the IP chip through the CPU chip. Therefore, in qualification and failure analysis of mass-produced MCPs, it was complicated and troublesome tasks and very inconvenient to analyze IP chips mounted in MCPs when some failures or degradation are found. More specifically, an easy method or a convenient structure that appropriate signals are directly supplied to the IP chip, without using the paths on the CPU chip, so as to separately analyze the failure mode of the IP chip are unknown and cannot be implemented. Similarly, in commercial products, when a defective product is found, and when the IP chip in the defective MCP must be analyzed, the failure cite and failure mechanism, etc. of the IP chip cannot be independently analyzed in the conventional MCP. As a result, the failure of the IP chip cannot be precisely analyzed, and it is extremely difficult to assess the electrical behavior of the IP chip and to study the reason for the failures occurred in the IP chip. Then considerably longer time is required to diagnose and analyze the failure site and failure mechanism, etc. of the IP chip.
In particular, in order to separately measure and inspect the electrical characteristics of the IP chip, the MCP must be decapsulated so that the IP chip can be remounted on a specific lead frame designed for testing as a single chip. This procedure is a difficult operation, which requires the closest attention and sophisticated technique, and disadvantageously spends longer time. In addition, it is disadvantageous because accidents such that the IP chips are broken, fractured or damaged at the remounting stage of the IP chips onto the single chip lead frames sometimes occur.